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CFD-TOPO: A Tool for Feature Scale Simulation of Semiconductor Processes Print E-mail

CFD-TOPO is a simulation tool that predicts how the shape of entities change due to the combined effects of chemical species transport and surface reactions at gas-solid interfaces. This application provides a wide array of tools to analyze the steps of a semiconductor process on the feature scale of a device (typically the order of micro-meter). Some of the different applications for CFD-TOPO include Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical vapor Deposition (PVD), Plasma Etching, and Sputtering.

CFD-TOPO has its own specialized graphical user interface and a separate solver. It is a "stand alone" simulation tool that gives you the option to independently model a problem or couple it with CFD-ACE+.

Typically in CFD-ACE+, one can have a system level global model involving flow, heat transfer, species transport, gas phase and surface reactions (i.e. a reactor model). The CFD-ACE+ model has an interface through which it can transfer the input data to a feature scale model. The input data for a feature scale model is the flux information at the inlet of a CFD-TOPO simulation.

The following few snapshots will demonstrate the basic capabilities of CFD-TOPO.

 

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If you are interested in learning more about CFD-TOPO, please send an email to This e-mail address is being protected from spam bots, you need JavaScript enabled to view it or contact your sales representative.

Abhra Roy
Senior Applications Engineer
ESI CFD Customer Support

 

CFD-TOPO: A Tool for Feature Scale Simulation of Semiconductor Processes

CFD-TOPO is a simulation tool that predicts how the shape of entities change due to the combined effects of chemical species transport and surface reactions at gas-solid interfaces. This application provides a wide array of tools to analyze the steps of a semiconductor process on the feature scale of a device (typically the order of micro-meter).

CFD-ACE+ and CFD-TOPO Coupling

There is a growing demand and challenge in different industries, especially semiconductor and MEMS areas, to have increased wafer size with reduced feature size, i.e. high quality process uniformity.


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